Prof. Taylor's Bespoke Silicon Group is working on the second version of their RISCV based open sourced GPGPU. A GPU extension over RV32 ISA is being developed to improve programmability and utilization of newly introduced hardware features.

Learn more

RV32 Extended GPU Instruction Set

Format Name Pseudocode
SDW rd rs1 rs2 Store from Double Word [rs1, rs2] <- rd
LDW rd rs1 rs2 Load from Double Word rd <- [rs1, rs2]