RISCV GPU ISA

Prof. Taylor's Bespoke Silicon Group is working on the second version of their RISCV based open sourced GPGPU. A GPU extension over RV32 ISA is being developed to improve programmability and utilization of newly introduced hardware features.

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RV32 Extended GPU Instruction Set

Format Name Pseudocode
SDW rd rs1 rs2 Store from Double Word [rs1, rs2] <- rd
LDW rd rs1 rs2 Load from Double Word rd <- [rs1, rs2]